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Course Unit Title Course Unit Code Type of Course Unit Level of Course Unit Year of Study Semester ECTS Credits
Advanced Digital Design MEH117 Elective Master's degree 1 Fall 8

Name of Lecturer(s)

Prof. Dr. Ali TANGEL
Associate Prof. Dr. Anıl ÇELEBİ

Learning Outcomes of the Course Unit

1) Understanding of programmable integrated circuit's architecture
2) To be able to design digital building blocks by using Verilog HDL
3) To be able to test digital systems
4) To be able to synthesize digital systems
5) To be able to understand the design flow from algorithm to hardware architecture
6) To be able to test digital systems on the FPGA development boards

Program Competencies-Learning Outcomes Relation

  Program Competencies
1 2 3 4 5 6 7
Learning Outcomes
1 Middle No relation No relation No relation No relation No relation No relation
2 No relation No relation No relation No relation No relation No relation No relation
3 No relation No relation No relation No relation No relation No relation No relation
4 No relation No relation No relation No relation No relation No relation No relation
5 No relation No relation No relation No relation No relation No relation No relation
6 No relation No relation No relation No relation No relation No relation No relation

Mode of Delivery

Face to Face

Prerequisites and Co-Requisites

None

Recommended Optional Programme Components

Digital Design

Course Contents

Introduction to VLSI Systems Design, Features and architectures of latest FPGAs of leading vendors, Detailed review of Digital Systems Design, Introduction to Verilog Design, Verilog coding of Combinational and Sequential Circuits, Writing a Test Bench, RTL Coding Guidelines, Design Flow for VLSI Systems and Design Methodology, Simulation, Synthesis, Place and Route and Back Annotation, Verilog Coding of Memories and Arithmetic Circuits, Development of Algorithms and Verification using High Level Languages, Architectural Design, VLSI Systems Design for a couple of projects.

Weekly Schedule

1) Introduction
2) Structural Modelling
3) Switch level Modeling
4) Data flow modeling. Behavioral modeling
5) Behavioral modelling.
6) Task/Function/UDPs
7) Hierarchical structural modeling. Advanced modelling.
8) Midterm examination/Assessment
9) Combinational & Sequential Logic Modules
10) System Design Methodology
11) Design options and system design methodology
12) Design Example-Bus & IO device
13) Design Examples: Microprocessor
14) Arithmetic modules
15) Synthesis. Verification. Design for testability
16) Final examination

Recommended or Required Reading

1- Digital System Designs and Practices: Using Verilog HDL and FPGAs Ming Bo Lin Wiley, ISBN: 978-0-470-82323-1, 2008
2- Advanced Digital Design with Verilog HDL Michael D. Ciletti Prentice Hall,ISBN: 0-13-167844-2,2003
3- Digital VLSI Systems Design, S. Ramachandran, Springer, 2007
4- Design Through Vrilog HDL, T. R. Padmanabhan, B. Bala Tripura Sundari, Wiley-IEEE, 2003
5- Embedded Media Processing, David J. Katz and Rick Gentile, Newnes, 2006
6- Verilog Coding for Logic Synthesis, WENG FOOK LEE, Wiley, 2003
7- Verilog Digital System Design, Zainalabedin Navabi, McGraw-Hill, 2006
8- Digital VLSI Systems Design, S. Ramachandran, Springer, 2007
9-
10-

Planned Learning Activities and Teaching Methods

1) Lecture
2) Discussion
3) Demonstration
4) Group Study
5) Problem Solving


Assessment Methods and Criteria

Contribution of Semester Studies to Course Grade

70%

 

Number

Percentage

Semester Studies

Laboratory

1

30%

Project

1

50%

Presentation/Seminar

1

20%

 

Contribution of Final Examination to Course Grade

30%

Total

100%

Language of Instruction

Turkish

Work Placement(s)

Not Required