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Course Unit Title | Course Unit Code | Type of Course Unit | Level of Course Unit | Year of Study | Semester | ECTS Credits |
---|---|---|---|---|---|---|
Controller Design With Vhdl | BTM504 | Elective | Master's degree | 1 | Spring | 8 |
Prof. Dr. Emine BOLAT
Research Assistant Seda BALTA
1) Performs a concurrent code in VHDL.
2) Performs sequential code in VHDL.
3) Designs a finite state machine in VHDL.
4) Designs packages and components in VHDL.
5) Performs functions and procedures in VHDL.
6) Designs a serial-parallel multiplier in VHDL.
7) Knows how to design a MAC(Multiply-Accumulate) circuit in VHDL.
8) Knows FPGA.
9) Does sample designs.
Program Competencies | ||||||||
1 | 2 | 3 | 4 | 5 | 6 | 7 | ||
Learning Outcomes | ||||||||
1 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
2 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
3 | No relation | No relation | No relation | High | No relation | No relation | No relation | |
4 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
5 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
6 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
7 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
8 | No relation | No relation | No relation | No relation | No relation | No relation | No relation | |
9 | No relation | No relation | No relation | No relation | No relation | No relation | No relation |
Face to Face
None
FPGA Based Digital System Design
Introduction to FPGA, design with VHDL, design simulation, design verification, implementation of the design with FPGA, examples of system designs.
Turkish
Not Required