Kocaeli University / European Credit Transfer System (ECTS)

Name of Lecturer(s)

Prof. Dr. Hüseyin Metin ERTUNÇ
Prof. Dr. Serdar KÜÇÜK
Associate Prof. Dr. Anıl ÇELEBİ
Assistant Prof. Dr. Öznur KÜÇÜKSARI
Research Assistant Dr. Ersin YOLAÇAN

Learning Outcomes of the Course Unit
Program Competencies-Learning Outcomes Relation

Learning Outcomes of the Course Unit

1) Understands the difference between the analog and digital concepts.
2) Designs coders and arithmetic modules based on the number systems used in computer systems.
3) Constructs logical equations based on Boolean algebra.
4) Designs digital circuits by using basic logical gates.
5) Knows the digital integrated circuits.
6) Applies the combinational logic circuit design fundamentals.
7) Analyzes the sequential logic circuits.
8) Designs finite state machines.
9) Models digital circuits by using hardware description languages (HDL).

Program Competencies-Learning Outcomes Relation

Program Competencies

Learning Outcomes

Low

No relation

Low

No relation

Mode of Delivery

Face to Face

Prerequisites and Co-Requisites

None

Recommended Optional Programme Components

Math 1

Course Contents

This course covers ; analog and digital signals, number systems, coding, binary numbers, binary arithmetics, digital logic circuits, Boolean algebra, logic design, Karnough maps, integrated circuits, combinational logics, flip flops, sequential logic, digital devices, counters, finite state machines, hardware description languages, registers and memories.

Weekly Schedule

1) Introduction
2) Combinational logic design
3) Decoders and muxes. Combinational logic design with Verilog/VHDL/C/C++.
4) Sequential logic circuits, latches and, flip-flops.
5) Sequential logic design with Verilog/VHDL/C/C++. Lab discussion. Announcement of final projects
6) Sequential logic circuits: Finite state machines and non-ideal behaviours.
7) Sequential logic design with Verilog/VHDL/C/C++ and lab discussion
8) Midterm examination Assessment
9) Sequential logic design with Verilog/VHDL/C/C++ and lab discussion.
10) Datapath components: Multifunction registers, adders, incrementer, comparators. Lab discussion.
11) -
12) Datapath components: ALU and register files. Datapath component desgn with Verilog/VHDL/C/C++. Lab discussion.
13) -
14) RTL design: Examples, memories and hierarchy. Lab discussion
15) Optimisation: Combinational logic optimisation, Karnaugh maps and tabular optimisation(Quine McCluskey method), sequential logic optimisation, datapath component tradeoffs.
16) Final examination Final project presentations

Planned Learning Activities and Teaching Methods

1) Lecture
2) Question-Answer
3) Discussion
4) Drill and Practice
5) Drill and Practice
6) Drill and Practice
7) Demonstration
8) Demonstration
9) Demonstration
10) Group Study
11) Group Study
12) Simulation
13) Case Study
14) Case Study
15) Case Study
16) Lab / Workshop
17) Self Study
18) Problem Solving
19) Project Based Learning

Assessment Methods and Criteria

Contribution of Semester Studies to Course Grade

70%

		Number	Percentage
Semester Studies	Midterm Examination	1	30%
	Laboratory	1	20%
	Project	1	40%
	Presentation/Seminar	1	10%

Contribution of Final Examination to Course Grade

30%

Total

100%

Language of Instruction

English

Work Placement(s)

Not Required

Course Unit Title	Course Unit Code	Type of Course Unit	Level of Course Unit	Year of Study	Semester	ECTS Credits
Digital Design	MUH207	Compulsory	Bachelor's degree	2	Fall	5