Computer Architecture

Mode of Delivery

Face to Face

Prerequisites and Co-Requisites

None

Recommended Optional Programme Components

Digital Design

Course Contents

This course covers digital abstraction, binary numbers, bits, bytes, nibbles and logic gates, logic levels, K-maps, finite state machines, hardware description languages. Metastability concept. Computer arithmetic review such as comparators, ALU. Fixed and floating point number systems and arithmetic operations in these domains. Review of sequential building blocks such as counter shift register, memory arrays, RAMs, ROMs. Review of logic arrays, transmission lines. MIPS instruction set and registers. Branches & procedure calls, addressing modes, linking & launching applications, single cycle processor data-path, single cycle processor control, multi-cycle processor, exceptions, pipelining, pipelining hazards and stalls, memory mapped I/O, memory system performance, & hierarchy,: caches, memory system optimization, virtual memory, advanced architecture.

Weekly Schedule

1) Introduction: digital abstraction; binary numbers; bits, bytes, and nibbles; logic gates. Logic Levels; Transistor-level implementation; truth tables, Boolean expressions; Boolean Algebra
2) K-maps; X’s and Z’s; multiplexers and decoders; priority encoders. Timing. Hazards. Sequential circuits: SR latches, D latches, flip-flops, clocking
3) Finite State Machines. Introduction to Hardware Description Languages (HDLs): Verilog
4) More Verilog. Dynamic disiplin.
5) Arithmetic: adders, subtractors, comparators, ALU’s. Number systems: fixed & floating point. Arithmetic: multiplication
6) Sequential Building Blocks: counter, shift register. Memory Arrays: RAMs, ROMs. Logic Arrays: PLAs, FPGAs
7) Transmission Lines. MIPS Instruction Set and Registers.
8) Midterm examination/Assessment
9) Branches & Procedure Calls, Addressing Modes. Linking & Launching Applications.
10) Single-Cycle Processor Datapath. Single-Cycle Processor Control.
11) Multicycle Processor. Exceptions.
12) Pipelining. Pipelining hazards and stalls.
13) Memory-mapped I/O
14) Memory system performance & hierarchy: Caches.
15) Memory system optimization; Virtual Memory
16) Final examination

Recommended or Required Reading

1- Carl Hamacher, Computer Organization and Embedded Systems
2- Sarah L. Harris and David Harris, Digital Design and Computer Architecture, RISC-V Edition

Planned Learning Activities and Teaching Methods

1) Lecture
2) Question-Answer
3) Discussion
4) Demonstration
5) Demonstration
6) Demonstration
7) Group Study
8) Group Study
9) Group Study
10) Simulation
11) Lab / Workshop
12) Self Study
13) Self Study
14) Self Study
15) Problem Solving
16) Project Based Learning

Assessment Methods and Criteria

Contribution of Semester Studies to Course Grade	70%
Number Percentage Semester Studies Laboratory 1 30% Project 1 50% Presentation/Seminar 1 20%
Contribution of Final Examination to Course Grade	30%
Total	100%

Language of Instruction

Turkish

Work Placement(s)

Not Required