Functional Verification of Digital Integrated Circuits

Mode of Delivery

Face to Face

Prerequisites and Co-Requisites

None

Recommended Optional Programme Components

Advanced Digital Design

Course Contents

Topics include the fundamentals of simulation based functional verification, stimulus generation, results checking, coverage and debug.

Weekly Schedule

1) Introduction to Verification
2) System Verilog Language Constructs
3) System Verilog Language Constructs
4) Procedures, Tasks and Functions. Connecting the Testbench and Design
5) Procedures, Tasks and Functions. Connecting the Testbench and Design.
6) Object Oriented Programing
7) Randomization
8) Midterm examination/Assessment
9) Randomization. Threads and Inter-process Communication.
10) Threads and Inter-process Communication.
11) Functional Coverage
12) SystemVerilog Assertions
13) SystemVerilog Assertions
14) Advanced Interfaces
15) Advanced OOP and Testbench Guidelines
16) Final examination

Recommended or Required Reading

1- Spear, C. and Tumbush, G.SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 3rd Edition
2- IEEE, IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language. New York: IEEE, 2009 (a.k.aSystemVerilog Language Reference Manual, or LRM)

Planned Learning Activities and Teaching Methods

1) Lecture
2) Discussion
3) Demonstration
4) Group Study
5) Problem Solving

Assessment Methods and Criteria

Contribution of Semester Studies to Course Grade	70%
Number Percentage Semester Studies Laboratory 1 30% Project 1 50% Presentation/Seminar 1 20%
Contribution of Final Examination to Course Grade	30%
Total	100%

Language of Instruction

Turkish

Work Placement(s)

Not Required